Typically, a cache subsystem comprises two or more levels within a cache hierarchy, a higher cache memory and a lower cache memory. The cache hierarchy may be such that a plurality of lower memories is assigned to a higher memory.
Within these systems, the cache is organized in cache lines. Cache lines represent a certain segment of an address range and the idea of cache lines is based on the principle of spatial locality. Cache lines are replaced from time-to-time for several reasons.
The higher cache memory is not updated by lower cache memory replacements. A cache line present in the lower cache memory shall also be in the higher cache memory (super-set rule), but an entry marked “lower cache memory-valid” in the higher cache memory may or may not be in the lower cache memory. Actually, the higher cache memory does not know which lines were already replaced within the lower cache memory.
In order to solve the problem that lower cache memory and higher cache memory get inconsistent, cache coherency protocols were developed in the past.
Within such a protocol the higher cache memory sends so called cross interrogate commands (XI) to the lower cache memory to control the state of the cache lines present in the lower cache memory.
XI commands may comprise ‘invalidate’ (forcing the state to invalid “I-State”), or ‘demote to shared’ (“S-State”).